1. Field of the Invention
The present invention relates to a demultiplexer for a digital time-division multiplex communication system wherein a digital signal which is asynchronous with the pulse frame and consists of successive blocks whose beginnings are marked with sync words is inserted into the pulse frame.
2. Description of the Prior Art
Such a synchronizing circuit contained in a demultiplexer is disclosed in DE-A1-34 39 633. In the demultiplexer described there, the sync signal is derived from the clock of the received sync words by correcting the word clock with the aid of additional information transmitted to the demultiplexer, such that the intervals between successive clock pulses are equal to the intervals between the sync words of the digital signal to be inserted into the pulse frame by the multiplexer at the transmitting end, which are asynchronous with the pulse frame. The jitter of the sync words caused by the asynchronous insertion of this signal, also referred to as "waiting-time jitter", is thus clearly reduced in the demultiplexer.
This solution has the disadvantage that a circuit for generating the additional information is required at the transmitting end, and that through the transmission of this additional information, the amount of useful information that can be transmitted is reduced.